A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks

Convolutional Neural Networks (CNN) are widely employed in the contemporary artificial intelligence systems. However these models have millions of connections between layers, that both memory prohibitive and computationally expensive. Employing on an embedded mobile application is resource limited with high power consumption significant bandwidth requirement to access data from off-chip DRAM. Reducing movement on-chip DRAM main criteria achieve throughput overall better energy efficiency. Our proposed multi-bit accelerator achieves goals by employing truncation partial sum (Psum) results preceding layer before feeding it into next layer. We exhibit architecture inferencing 32-bits for first convolution layers sequentially truncate bits MSB/LSB integer fractional part without any further training original network. At last fully connected layer, top-1 accuracy maintained reduced bit width 14 top-5 upto 10-bit width. The computation engine consists systolic array 1024 processing elements (PE). Large CNNs such as AlexNet, MobileNet, SqueezeNet EfficientNet were used benchmark CNN model Virtex Ultrascale FPGA was test architecture. scheme has 49% reduction utilization 73.25% LUTs (Look-up tables), 68.76% FFs (Flip-Flops), 74.60% BRAMs (Block RAMs) 79.425% Digital Signal Processors (DSPs) when compared 32 design a performance 223.69 GOPS FPGA, gain 3.63 × other prior accelerators. In addition, 4.5 lower architectures. ASIC version designed 22nm FDSOI CMOS process 2.03 TOPS/W total 791 mW area 1 mm 1.2 mm.